1. Field of the Invention
This invention relates to microprocessors, and more particularly, to efficiently reducing the latency and power of register renaming.
2. Description of the Relevant Art
Microprocessors typically include overlapping pipeline stages and out-of-order execution of instructions. Additionally, microprocessors may support simultaneous multi-threading to increase throughput. Microprocessor throughput may be measured by the useful execution of a number of instructions per thread for each stage of a pipeline. These techniques take advantage of instruction level parallelism (ILP) and may increase the throughput. However, these techniques generally add more hardware and more depth to a pipeline. In addition, control dependencies and data dependencies associated with such techniques may reduce a maximum throughput of the microprocessor.
Speculative execution of instructions is used to perform parallel execution of instructions despite control dependencies in the source code. In a software application, straight line code is a group of instructions without branches, loops, or tests that may be sequentially executed, although implemented hardware may perform out-of-order processing of instructions. Straight line code may also be referred to as a basic block of instructions. In straight line code, read after write (RAW), write after read (WAR) or write after write (WAW) dependencies may be encountered. Register renaming may be used to allow parallel execution of instructions despite the WAR and WAW dependencies. The execution techniques used to increase throughput may utilize a relatively large number of non-architectural registers which may be referred to as “physical registers”.
Physical registers are typically used to store the state of intermediate results from instruction execution after eliminating false write after read (WAR) dependencies and re-ordering write after write (WAW) dependencies in the pipeline. A free list is used to keep track of which physical registers are not currently in use. These particular free physical registers are available for use by incoming instructions. As the number of physical registers increase, the number of storage elements used for the free list and for identifying recently retired physical register identifiers increases. Therefore, on-die real estate, clock signal loading, signal cross-capacitance, and as a result, power may increase for the maintenance of these physical registers.
In view of the above, methods and mechanisms for reducing the latency and power of register renaming are desired.